<?xml version='1.0' encoding='UTF-8'?><?xml-stylesheet href="http://www.blogger.com/styles/atom.css" type="text/css"?><feed xmlns='http://www.w3.org/2005/Atom' xmlns:openSearch='http://a9.com/-/spec/opensearchrss/1.0/' xmlns:georss='http://www.georss.org/georss' xmlns:gd='http://schemas.google.com/g/2005' xmlns:thr='http://purl.org/syndication/thread/1.0'><id>tag:blogger.com,1999:blog-896357216157955555</id><updated>2011-11-27T17:01:54.615-08:00</updated><title type='text'>Scott Kellerman</title><subtitle type='html'>I have been employed as a Digital Logic Designer for over 15 years specializing in FPGA and embedded DSP designs. I have broad experienced in all phases of board level design from concept through production release and has a demonstrated proficiency in the design of complex high-speed FPGAs using Verilog and VHDL, creating test benches, TCL/Perl scripts, and C code for timing driven simulation, logic verification and synthesis of FPGA and PLD designs.</subtitle><link rel='http://schemas.google.com/g/2005#feed' type='application/atom+xml' href='http://scottkellerman.blogspot.com/feeds/posts/default'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/896357216157955555/posts/default?max-results=100'/><link rel='alternate' type='text/html' href='http://scottkellerman.blogspot.com/'/><link rel='hub' href='http://pubsubhubbub.appspot.com/'/><author><name>Scott Kellerman</name><uri>http://www.blogger.com/profile/08052265528220548592</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='http://img2.blogblog.com/img/b16-rounded.gif'/></author><generator version='7.00' uri='http://www.blogger.com'>Blogger</generator><openSearch:totalResults>1</openSearch:totalResults><openSearch:startIndex>1</openSearch:startIndex><openSearch:itemsPerPage>100</openSearch:itemsPerPage><entry><id>tag:blogger.com,1999:blog-896357216157955555.post-8889794054868509764</id><published>2009-03-04T03:42:00.000-08:00</published><updated>2009-03-04T03:44:07.688-08:00</updated><title type='text'></title><content type='html'>&lt;div&gt;CISCO SYSTEMS INC – SAN JOSE CA AND BRADENTON FL - 1999 - Present&lt;/div&gt;&lt;div&gt;Hardware Design Engineer III&lt;/div&gt;&lt;div&gt;Responsible for design and development of high-speed digital circuit boards for Gigabit Ethernet switching and routing applications using embedded processors, DSPs, FPGAs, custom ASICs and high speed, low voltage discrete logic. Created Functional Specifications, cost estimates, time-to-completion estimates, parts lists, schematics, and other documentation.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;Design contributions at Cisco include:&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;* 802.3at PoE PSE daughter card for 48 port GigE blade (Project Name: Alafia)&lt;/div&gt;&lt;div&gt;* 802.3af PoE PSE daughter card (Project Name: Luhai)&lt;/div&gt;&lt;div&gt;* Test platform for 144Mb, 6.25GHz, SerDes based Network Memory ASICs implementing Xilinx Virtex 4 and Vitex 5 FPGAs. (Project Name: Ratchet)&lt;/div&gt;&lt;div&gt;* 802.3af/at PD Emulation platform for real-time, standards based PSE verification - First in Industry. (Project Name: Terminus &amp;amp; Terminus3)&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;Digital Design Engineer at SENTIENT NETWORKS - SAN JOSE CA&lt;span class="Apple-tab-span" style="white-space:pre"&gt; &lt;/span&gt;- 1995 - 1999&lt;/div&gt;&lt;div&gt;Contributed to the design of a digital printed circuit boards for Gigabit Ethernet switching applications. Specifically; the embedded Intel I960 processor sub-systems and VHDL FPGA, and AHDL PLD designs. Designed and wrote the board and system level power-on diagnostics. Created schematics, performed FPGA and board level VHDL simulation, verification and synthesis.         Sentient Networks was eventually sold to Cisco Systems.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;1995 and earlier&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;At FAIRCHILD WESTON/LORAL DATA SYSTEMS, (now L3), held the following positions:&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;SR. TELEMETRY ENGINEERING SPECIALIST, TELEMETRY SYSTEMS - SARASOTA FL&lt;/div&gt;&lt;div&gt;FPGA, PLD, and printed circuit board design for the CPS100 Telecom Switch Program. Created Schematic and performed gate-level simulation, debug, and design verification.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;R &amp;amp; D ENGINEERING, AVIATION FLIGHT RECORDERS – SARASOTA, FL&lt;/div&gt;&lt;div&gt;Design, simulated and debugged FPGA, and PLD design for commercial aviation flight recorders including the first generation of solid-state recorders. Created schematics and BOM’s.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;TELEMETRY SYSTEMS ENGINEER, TELEMETRY SYSTEMS - SARASOTA FL&lt;/div&gt;&lt;div&gt;Designed, developed, and installed a multi-rack ‘Majority Vote’ launch data acquisition and control system for Lockheed Martin's Titan IV launch platform.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;FIELD SERVICE ENGINEER, TELEMETRY SYSTEMS – SACRAMENTO CA&lt;/div&gt;&lt;div&gt;Providing technical support, training, and maintenance for a Flight Data Acquisition and Test system (FDAT) created for the USAF F111 Aircraft Modernization Program (AMP)&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;SR. ENGINEERING TEST TECHNICIAN, SIGNAL PROCESSING SYSTEMS (SPS) - SARASOTA FL&lt;/div&gt;&lt;div&gt;Test, verification, and component level repair of NSA classified telemetry acquisition and analysis platforms. PCM/FSK-AM/PM, Spread Spectrum, etc.&lt;/div&gt;&lt;div&gt;*&lt;span class="Apple-tab-span" style="white-space:pre"&gt; &lt;/span&gt;NSA/DoD secret clearance, Supervised 6 technicians.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;Earlier experience&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;Computer Administrator, THE NEWS AND OBSERVER, RALEIGH, NC&lt;/div&gt;&lt;div&gt;Systems Test, EXIDE TECHNOLOGIES, RALEIGH, NC&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;Military Experience &lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;AVIATION ELECTRICIANS MATE, PETTY OFFICER 2ND CLASS, UNITED STATES &lt;/div&gt;&lt;div&gt;Flight deck troubleshooter - Maintained and repaired Grumman A6E Intruder aircraft electrical distribution systems, engine and flight controls, and instrumentation systems.&lt;/div&gt;&lt;div&gt;Attended Navy A &amp;amp; B schools, BE&amp;amp;E, AE A school, Aircraft Instrumentation.&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div&gt;Education: WAKE COUNTY COMMUNITY COLLEGE, RALEIGH, NC: Computer Sciences&lt;/div&gt;&lt;div&gt;&lt;br /&gt;&lt;/div&gt;&lt;div class="blogger-post-footer"&gt;&lt;img width='1' height='1' src='https://blogger.googleusercontent.com/tracker/896357216157955555-8889794054868509764?l=scottkellerman.blogspot.com' alt='' /&gt;&lt;/div&gt;</content><link rel='replies' type='application/atom+xml' href='http://scottkellerman.blogspot.com/feeds/8889794054868509764/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://scottkellerman.blogspot.com/2009/03/cisco-systems-inc-san-jose-ca-and.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/896357216157955555/posts/default/8889794054868509764'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/896357216157955555/posts/default/8889794054868509764'/><link rel='alternate' type='text/html' href='http://scottkellerman.blogspot.com/2009/03/cisco-systems-inc-san-jose-ca-and.html' title=''/><author><name>Scott Kellerman</name><uri>http://www.blogger.com/profile/08052265528220548592</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='http://img2.blogblog.com/img/b16-rounded.gif'/></author><thr:total>0</thr:total></entry></feed>
